This invention relates to a method of making high capacitance per unit area charge storage capacitors and rectifiers for a voltage multiplier, and more particularly, to polysilicon-insulator-polysilicon capacitors and polysilicon-insulator-semiconductor enhancement mode field effect transistors that are compatible with conventional monolithic double level polysilicon integrated circuit fabrication.
MNOS and its silicon gate counterpart SNOS (hereafter MNOS includes SNOS and vice versa) technology is now well-established for constructing nonvolatile memory integrated circuits. Because of its excellent memory operational characteristics MNOS technology is experiencing increasing application to various types of semiconductor integrated circuit memory arrays such as E.sup.2 PROMs and NVRAMs. One disadvantage of the technology, which has somewhat restricted its application, is the requirement of high (of the order of 25 volts or more) program (i.e. write and erase) voltages necessitating dual polarity (+ and -) external power supplies.
The goal of the microelectronics industry is to use a single 5 volt external power supply and generate, on-chip, the high erase and write voltages thereby eliminating the need for multiple external power supplies and making the MNOS devices econonically more viable. One method of on-chip high-voltage generation is by means of the voltage multiplier technique. One such prior art voltage multiplier scheme is shown in FIGS. 1A and 1B which represent circuits for generating a high positive voltage and low negative voltage, respectively.
Referring to FIG. 1A, V.sub.CC represents the input power supply voltage, typically 5 volts and V.sub.OUT is the voltage output of the positive voltage multiplier. V.sub.OUT &gt;&gt;V.sub.CC. C.sub.1, C.sub.2 . . . C.sub.n are coupling capacitors and Q.sub.1, Q.sub.2 . . . Q.sub.m are rectifying elements (or diodes). In this prior art voltage multiplier arrangement, the capacitors were typically depletion mode MOS or MNOS transistors and the rectifying elements were diode-connected enhancement mode MOS transistors.
Referring to FIG. 1B, V.sub.g here represents the ground connection and V'.sub.OUT is the voltage output of the negative voltage multiplier. V'.sub.OUT &lt;&lt;V.sub.g. As in FIG. 1A, C'.sub.1, C'.sub.2 . . . C'.sub.n and Q'.sub.1, Q'.sub.2 . . . Q'.sub.m represent coupling capacitors and diodes, respectively. The significant difference between the prior art schemes shown in FIGS. 1A and 1B is that the depletion mode transistors C'.sub.1, C'.sub.2 . . . C'.sub.n shown in FIG. 1B are connected in a direction reverse to that of devices C.sub.1, C.sub.2 . . . C.sub.n in order to generate the low-negative voltages at each successive node of the diode chain and to ensure that these negative voltages do not turn off transistors C'.sub.1, C'.sub.2 etc.
.phi..sub.1 and .phi..sub.2 shown in FIG. 1A and .phi..sub.1 ' and .phi..sub.2 ' shown in FIG. 1B designate two clock pulses, of the type shown in FIG. 2, having a fixed amplitude and in antiphase with each other. These pulses are applied to the successive nodes of the diode-chain via the coupling capacitors. The amplitude of these clock pulses is typically about 5 volts.
Using the voltage multiplier circuit shown in FIG. 1A, in the publication entitled "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using An Improved Voltage Multiplier Technique" by J. F. Dickson and published in IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976, pp. 374-378, it was demonstrated that it is possible to generate, on-chip, high-voltages of up to +40 volts to enable operation of MNOS integrated circuits. In this publication, the coupling capacitors appear to be depletion mode transistors which were implemented using the nitride dielectric available in the MNOS process and the diodes were MOS transistors.
A drawback of positive and negative voltage multiplier circuits which use depletion mode transistors as coupling capacitors is that they cannot be conveniently used for generating high positive and low negative voltages at the same (output) node. This ability is essential for an on-chip voltage multiplier since devices on an I.C. chip such as NV RAMs invariably require that the same node of the voltage multiplier go both positive and negative. In other words, in order to generate the required voltages, on-chip, the output nodes V.sub.OUT and V'.sub.OUT of FIGS. 1A and 1B, respectively, need to be connected and this common node be used for programming the devices on the chip. However, when the outputs V.sub.OUT and V'.sub.OUT of the prior art voltage multiplier circuits which used depletion mode transistors for capacitors are connected together, voltage multiplication is severely hampered, if not, destroyed, since such an arrangement will turn off many of these depletion mode devices. For example, if the (negative) output V'.sub.OUT of FIG. 1B is connected to the (positive) output V.sub.OUT of FIG. 1A then this negative voltage, when applied via the diode Q.sub.m to the gate of the depletion transistor C.sub.n, will turn off C.sub.n. Likewise, when this negative gate voltage of C.sub.n is applied, via diode Q.sub.m-1 to the gate of the transistor C.sub.n-1, it will turn off C.sub.n-1 and so on. Thus, a number of depletion mode devices C.sub.n, C.sub.n-1 . . . will turn off rendering the positive voltage multiplier non-functional. A similar hampering of the negative voltage multiplier (FIG. 1B) operation will occur if (the positive) node V.sub.OUT is connected to (the negative) node V'.sub.OUT.
One way of overcoming the above voltage multiplier problem is by not connecting together V.sub.OUT and V'.sub.OUT and discharging these output nodes separately. However, this necessitates two separate discharging circuits.
Another way of overcoming the above voltage multiplier operation problems when the output nodes of the positive and negative multiplier are connected together, is by eliminating the depletion mode devices altogether and using in their place permanent capacitors. Since operation of permanent capacitors is not dependent upon the polarity of the voltage applied across their plates, it is possible to connect together the output nodes of the positive and negative multipliers without affecting the performance of either. However, fabrication of such permanent capacitors, on-chip, require additional cumbersome processing steps in the prior art single level silicon or metal MNOS process by virtue of limitations of the MNOS process. The cost of these additional steps may outweigh the benefit of building, on-chip, dual polarity voltage multipliers in these earlier MNOS processes.
It is an object of this invention to form permanent capacitors, for use in on-chip dual polarity voltage multiplier construction, using the conventional double level silicon SNOS process for fabricating passive devices and active memory and non-memory devices without additional process or mask steps.
It is another object of this invention to form parallel high conductivity polysilicon plate capacitors by using a single doping step to simultaneously dope both the upper and lower polysilicon plates.
It is another object of this invention to form high capacitance per unit area polysilicon-insulator-polysilicon capacitors simultaneously with silicon gate MOS enhancement mode transistors for use as elements of an on-chip positive and negative voltage multiplier.
These and other objects of the invention will be apparent from the following description.